DAC_EN=Val_0x0, DAC_INPUT_BYP_MUX_EN=Val_0x0, DAC_RESET_B=Val_0x0, DAC_HP_MODE_EN=Val_0, DAC_TWOSCOMP_EN=Val_0x0
REG1 DAC Control Register
| DAC_EN | DAC enable: 0 (Val_0x0): DAC is disabled 1 (Val_0x1): DAC is enabled |
| DAC_INPUT_BYP_MUX_EN | Selects DAC input data source: 0 (Val_0x0): DAC_IN register 1 (Val_0x1): DAC_REG1[DAC_BYP_VAL] bitfield (bypass mode) |
| DAC_BYP_VAL | DAC input data in bypass mode |
| DAC_CAP_CONT | Trims HP mode capacitance compensation: From xx00 = 2 pF to xx11 = 8 pF Step size = 2 pF Default is xx11 = 8 pF for DAC120 and xx00 for DAC121 Bits [17-16] = Don’t care |
| DAC_HP_MODE_EN | DAC high-performance mode enable. 0 (Val_0): Low-power (LP) mode (default for DAC121) 1 (Val_1): High-performance (HP) mode (default for DAC120) |
| DAC_TWOSCOMP_EN | Converts two’s complement to unsigned binary data: 0 (Val_0x0): Input data is unsigned 1 (Val_0x1): Input data is two’s complement signed (conversion to unsigned enable) |
| DAC_IBIAS | Trims buffer output current (HP mode): From 0000 = 0 uA to 1111 = 1.5 mA Default is 1111 for DAC120 and 0000 for DAC121 Step size ~100 uA |
| DAC_RESET_B | DAC reset: 0 (Val_0x0): Reset asserted 1 (Val_0x1): Reset released |